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U4050B
Speech Circuit with Line-Powered Loudspeaker Amplifier
Description
The electronic speech circuit U4050B is a linear integrated circuit for use in telephone sets. It replaces the hybrid transformer, sidetone equivalent and ear protection rectifiers. The circuit is line powered and contains all components necessary for amplification of signals and adaptation to the line. An integrated loudspeaker amplifier allows loudhearing operation.
Features
D Integrated amplifier for loudhearing operation D Anticlipping for loudspeaker amplifier D Supply voltages for all functional blocks of a
subscriber set
D D D D D D D
D D D D
DTMF and MUTE inputs Anticlipping in transmit direction Squelch Integrated transistor for short circuiting the line voltage
Adjustable DC characteristics Adjustable sending and receiving amplification Automatic line loss compensation Symmetrical output of earpiece amplifier Built-in ear protection Symmetrical input of microphone amplifier Adjustable sidetone suppression independent of sending and receiving amplification
D Power down D Operation possible at line currents above 10 mA
Benefits
D Independent adjustment of transmit gain, receive gain
and sidetone suppression
D Low number of external components
Block Diagram
GS
9
MICO
7
TIN
15
ST
4 +
GR
2 - +
RECO1
3
RECO2
1
DTMF MIC1 MIC2
8 - 10 11 +
-
SAI
26
GSA SAO CLISA AGA CK VL RDC VC
SA
21
LIMSA LEVSQ CSQ
12 13
17 27 6
SQUELCH
TXA
AGA REC. ATT.
23
LIMITER NSA MUTE
5 16 25
Power supply
19
U4050B
24 22 28 18 14 20
CLIM
MUTE
PD
GND IREF SWAMP VM
VD
Figure 1. Block diagram
Ordering Information
Extended Type Number U4050B-AFL U4050B-AFLG3 Package SO28 SO28 Remarks Taped and reeled
Rev. A2, 05-Mar-98
1 (18)
U4050B
Block Diagram / Application Circuit
With a squelch function, acoustical feedback during loudhearing can be reduced significantly. The generated
2 (18)
CNW2 22n RNW3
VM
Sidetone network
3.3k RNW2 1k + CGR 2.2 m CNW1 100n RNW1 27k RR1 15k CTIN 100n RR2 390 RS2 300 12k RS1
VM
DTMF GS MICO TIN ST
15 3 - + + - + 21 - RGSA 100k 4 2 1
GR
RECO1
RECO2
CDTMF 100n 9 7
RDTMF
DTMF 8
20k
MIC1 10 SAO
SAI SA
CSAO 47m + CLISA 4.7m
26
GSA
MIC2
11
RL 50
RSQ 100k 17 27 6
LIMSA TXA REC. ATT. AGA
LEVSQ 12
CLISA AGA CK CK
150n
+
CSQ 13
SQUELCH
CSQ 1m
+
RAGA 7.5k
LINE
23
Figure 2. Typical application diagram
VL RDC
10 19 +
LIMITER NSA MUTE
5 16 25 22 28 18
Power supply
RDC
24 14 20
U4050B
VC VM
+ 39 CM 22 m
CC 10m RIMP 1k
CLIM MUTE
PD IREF
GND
SWAMP
RSWAMP
VD
RC >60k CIMP 10m + CD 1000 m
+
13V CL 68n
CLIM 470n
RREF 47k
MUTE
PD
direkt an Pin 22
supply voltage is suitable for a wide range of peripheral circuits.
Rev. A2, 05-Mar-98
93 7815 e
U4050B
Pin Description
RECO2 GR RECO1 ST CLIM CK MICO DTMF GS MIC1 MIC2 LEVSQ CSQ VM 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 IREF 27 AGA
Pin 11 12
Symbol MIC2 LEVSQ CSQ VM
26 GSA 25 PD 24 VC 23 VL 22 GND 21 SAO 20 VD 19 RDC
13 14
15 16 17 18
TIN MUTE CLISA SWAMP
18 SWAMP 17 16 15 CLISA MUTE TIN
14052
19
RDC
20
VD
Figure 3. Pinning S028
Pin 1 3 2
Symbol RECO2, RECO1 GR
4 5 6 7 8
ST CLIM CK MICO DTMF
9
GS
10
MIC1
Function Symmetrical outputs of receiving amplifier A resistor connected from this pin to VM (AC coupled) sets the receiving amplification at the circuit Input of sidetone amplifier Time constant of anticlipping in transmit patch Input of receiving path Output of microphone preamplifier Input for DTMF signals (ac coupled). In Mute condition a small portion of the signal at this pin is monitored to the receiver output. A resistor from this pin to VM sets the amplification of microphone and DTMF signals. Inverting input of microphone amplifier
21 22 23 24
SAO GND VL VC
25
PD
26 27
GSA AGA
28
IREF
Function Non-inverting input of microphone amplifier Input for setting the switching level of the squelch circuit Time constant of the squelch function Reference node for microphone, earphone and loudspeaker amplifier. Supply for electret microphone set to VD/2. Input of intermediate transmit stage Active high input to switch the circuit into DTMF condition. Time constant of anticlipping of speaker amplifier. A resistor connected from this pin to ground converts the excess line current into heat in order to prevent the IC from thermal destruction at high line currents A small resistor connected from this pin to VL sets the slope of the characteristic and also affects the line length equalization characteristics and the line current at which the loudspeaker amplifier is switched on. Unregulated supply voltage for peripheral circuits (dialers, microprocessors, etc.). Output current capability and output voltage increase with line current. Output of loudspeaker amplifier. Reference point for DC and AC output signals Line voltage The internal equivalent inductance of the circuit is proportional to the value of the capacitor at this pin. A resistor connected to ground may be used to reduce the line voltage. Active high input for reducing the current consumption of the circuit. Simultaneously VL is shorted by an internal switch. Current input for setting the gain of the speaker amplifier Automatic gain adjustment with line current. A resistor connected from this pin to VL sets the starting point. Maximum gain change is 6 dB. Internal reference current generation
Rev. A2, 05-Mar-98
3 (18)
U4050B
Absolute Maximum Ratings
Parameters Line current Line voltage Junction temperature Ambient temperature Storage temperature Total power dissipation (Tamb = 60C, SO28) Symbol IL VL Tj Tamb Tstg Ptot Value 140 15 150 -25 to +75 -55 to +150 750 Unit mA V C C C mW
Thermal Resistance
Parameters Junction ambient SO28 Symbol RthJA Value 120 Unit K/W
Electrical Characteristics
Test conditions unless otherwise specified: f = 1 kHz, 0 dBm = 775 Vrms, IM = 0.3 mA, ID = 2 mA, RC = 130 k, Tamb = 25C, RGSA = 560 k, ZH = ZM = 68 nF, Pin AGA open Parameters DC characteristics Test Conditions / Pins Symbol see figure 4 IL = 2 mA VL IL = 15 mA VL IL = 19 mA VL IL = 30 mA VL IL = 100 mA VL see figures 5 and 11 IL = 15 mA IL = 15 mA IL 15 A, CL = 4.7 nF f = 300 to 3400 Hz Pin AGA open IL = 15 to 100 mA Tamb = - 10 to + 60C IL = 15 mA GS Min. Typ. 1.9 5.2 5.4 6.0 9.5 Max. Unit V V V V V
DC voltage drop oltage over circuit
4.8
5.6
Transmission amplifier Adjustment range of transmit gain Transmitting amplification Frequency response Gain change with current Gain deviation CMRR of microphone amplifier Input resistance of MIC amplifier Distortion at line Maximum output voltage Noise at line psophometrically weighted Anticlipping attack time Release time
40 47.75
48 48.25
56
dB dB dB
w
DGS DGS DGS
CMRR Ri
GS
"0.5 "0.5 "0.5
80 2
48.75
dB dB dB k %
60 45
80 60
IL > 15 mA VL = 775 mV2rms IL > 19 mA d < 5% Vmic = 10 m IL > 15 mA GS = 48 dB Vmic = 20 mV C = 470 nF Each 3 dB overdrive
ds
V1max no
1.8
3 - 80
4.2 -72
dBm dBmp
0.5 9
ms ms
4 (18)
Rev. A2, 05-Mar-98
U4050B
Parameters Gain at low operating current Distortion at low operating current Line loss compensation Mute suppression Receiving amplifier Adjustment range of receiving gain Receiving amplification Amplification of DTMF signal from DTMF IN to RECO 1/2 Frequency response Gain change with current Gain deviation Ear protection differential Output resistance Line loss compensation Output voltage Push pull Single ended Receiving noise psophometrically weighted Gain at low operating current Test Conditions / Pins Symbol IL = 10 mA, ID = 1 mA RC = 68 k GS Vmic = 1 mV IM = 0 mA IL = 10 mA, IM = 0 mA ID = 1 mA, RC = 68 k ds Vmic = 10 mV IL = 100 mA DGSI RAGA = 7.5 k IL 15 mA GSM Vmute = 1.5 V see figures 6 and 8 IL 15 mA GR differential IL = 15 mA GR differential IF 15 mA GRM Min. 47 Typ. Max. 50 Unit dB
6 -5 60 -6 -7
% dB dB
w w
-8 -1 - 15 - 0.5 - 12
+8 0 -9
dB dB dB
w
Distortion at low operating current
Mute active IL > 15 mA, CL = 4.7 nF f = 300 to 3400 Hz IL = 15 to 100 mA Tamb = -10 to + 60C IL = 15 mA IL 15 mA Vgen = 11 Vrms Each output against GND IL = 100 mA RAGA = 7.5 k IL = 15 mA, d 2% ZH = 68 nF ZH = 450 ZH = 150 ZH = 68 nF GR = 0 dB IL > 15 mA IL = 10 mA ID = 1 mA IM = 0 mA Vgen = 560 mV RC = 68 k IL = 10 mA, ID = 1 mA Vgen = 560 mV RC = 68 k
DGRF DGR DGR
Vep Ro
w
"0.5 "0.5 "0.5
2.2 10 - 5.0 - 6.0 - 7.0
dB dB dB
Vrms dB
DGRI
v
0.775 0.6 0.3 ni - 83 - 78.5
Vrms
dBmp
GR
- 1.5
+ 0.5
dB
dr
5
%
Rev. A2, 05-Mar-98
5 (18)
U4050B
Parameters Speaker amplifier Minimum line current for operation Gain from VL to SAO Output power Test Conditions / Pins see figure 7 No ac signal IL 15 mA Vgen = 10 mV Load resistance RL = 50 d<5% Vgen = 300 mVrms IL > 15 mA IL = 20 mA IL > 15 mA (Input GSA open) IL = 15 mA Tamb = -10 to + 60C IL = 15 to 100 mA RAGA = 7.5 k IL = 15 to 100 mA IL = 15 mA VL = 0 dBm Pin GSA open IL = 15 mA f = 300 to 3400 Hz 20 dB overdrive Symbol ILmin GSA Min. 10.5 27.5 29 Typ. Max. 15 30.5 Unit mA dB
w
PSA PSA nsa
5 20 200
mW V dB dB MW dBm
Output noise Gain devitation Gain change with current Resistor for turning off speaker amplifier Maximum off-state Output voltage Gain change with frequency Attack time Release time Distortion
DGSA DGSA
RGSA VSAO 0.8 1.3
"1 "1.5
2 - 50
DGSA
tr tf 1 300
"1
5
dB ms ms %
IL = 15 mA dSAO Vgen = 300 mV DTMF - amplifier see figure 8 Test conditions: ID = 2 mA, IM = 0.3 mA, RAGA = 7.5 k, mute active Adjustment range of DTMF IL = 15 mA GD gain Load = 600 DTMF amplification IL = 15 mA GD Gain deviation IL = 15 mA GD Tamb = - 10 to 60C Input resistance Ri Distortion of IL 15 mA d DTMF signal VI = 0 dBm Gain deviation IL = 15 to 100 mA DGD with current RAGA = 7.5 k
18 24.5
26 26
34
dB dB dB k % dB
"0.5
30 2
27
w
20
25
"0.5
6 (18)
Rev. A2, 05-Mar-98
U4050B
Parameters Test Conditions / Pins Supply voltage see figure 4 Test conditions: VMIC = 10 mV; Tamb = -10 to 60C Output voltage IL = 15 mA ID = 2 mA RC = 68 k IL = 15 mA ID = 2 mA RC = 130 k IL = 100 mA ID = 0 mA Tamb = -10 to + 60C IM = 0.3 mA IL 15 mA RC = 130 k see figure 9 IL 15 mA Symbol Min. Typ. Max. Unit
VD
2.9
V
VD
3.1
V
VD
6.1
V
Supply voltage for an electret microphone Squelch Attenuation of transmit gain Attenuation of speaker amplifier Switching level of squelch Squelch disable MUTE input MUTE input current
w
VM
1.45
3.3
V
w I w 15 mA R = 18 to 560 k I w 15 mA RSQ = 100 k I w 15 mA
L GSA L L
DGS DGSA
Vmico RSQ IMUTE
8 7.5 6.5 0.5
10 10
12 12.5 10
dB dB mV M A
1 20
2 30
MUTE input voltage
PD input PD input current
Input voltage Current consumption
Voltage drop at VL
see figure 10 MUTE active IL > 15 mA VMUTE = VD Mute inactive IL > 15 mA Mute active IL > 15 mA see figure 10 PD active IL > 15 mA VPD = VD PD = active PD = inactive VD = VPD = 4.5 V PD = active IL= 15 mA IL = 15 mA PD = active IL=100 mA PD = active
VMUTE VMUTE 1.5
0,3 0,3
V V
IPD VPD VPD IDPD 2
20
50
A V V A
- 40
0.3 - 100
VL
1.5
V
VL
1.7
V
Rev. A2, 05-Mar-98
7 (18)
U4050B
8 (18)
CNW2 1n RNW2 2.2k RNW1 39k + ZH 68n S14 RR1 CTIN 150n TIN 7 15 3 1 RGSA 560k - + + - - + 21 SAO 4 2 ST GR RECO1 RECO2 RDUM1 1.34M 15k 200 ZH RR2 390 RNW4 3.3k RS2 RS1 12k 300 CGR 22m VM CNW1 220n GS 9 MICO
VM
DTMF
8
SAI LHV
26
GSA CSAO 220 m + CLISA 4.7U RLAUT 50
MIC1 10
Vmic
MIC2 11
LIMSA TXA SQUELCH AGA
C600 100m 17 27 6 CLISA AGA CK RAGA 7.5k CK 150n 23 VL RDC 10 19 RDC 24 VC CC 10 m + ZL 600 VL
S9
RSQ 100k LEVSQ 12
CSQ 13
CSQ 1m
+
+ RIMP 1k +
LIMITER Power supply NSA MUTE
5 16 25 PD GND IREF MUTE 22 28 SWAMP RSWAMP VMUTE 0.3V 0.3V CLIM 470n VPD RREF 47k 39 CLIM
U4050B
18 VM 14 VD 20 RC 130k + IM 300 m A + CM 22 m VM VD CD 470 m ID 2mA CIMP 100 m 13V CL 68n IL
Figure 4. Test circuit for supply voltage DC characteristics
Rev. A2, 05-Mar-98
93 7821 e
RSWAMP VMUTE 0.3 V DC VPD 0.3 V DC RREF 47k
A A
Rev. A2, 05-Mar-98
CNW2 1n RNW2 2.2k RNW1 39k + RNW4 3.3k 200 RR1 CTIN 150n 15k TIN RECO1 2 3 - + + - - 10 11 + 1 RGSA 560k RECO2 RDUM1 1.34M 7 15 4 ST GR RS2 RS1 12k 300 RR2 390 ZH 68n CGR 22 m VM CNW1 220n GS MICO 9
Vmic
S21
ZM 68n
VM
RNW 25k
RNW 25k
b
a
a'
b'
DTMF 8
S19
SAI
26
GSA
MIC1
LHV
21 SAO
CSAO 220 m + CLISA 4.7m
RLAUT 50
S17
MIC2
C600 100 m
S10
LIMSA TXA AGA
CSQ 13
RSQ 100k
LEVSQ 12
17 CLISA 27 6 AGA CK
+ Vl, ds, no, Vlm S18 CK 150n 23 VL RDC 10 19 RDC RAGA 7.5k ZL 600
SQUELCH
Figure 5. Test circuit for transmit amplifier
LIMITER NSA MUTE
5 16 25 PD GND MUTE CLIM
CSQ 1m
+
+ CC 10 m RIMP 1k
Power supply
U4050B
24 22 IREF 14 VM VD 18 28 SWAMP 20 RC 130k + 39 IM 300 m A + CM 22 m CD 470 m ID 2 mA VC
+ CIMP 100 m 13V CL 68n
IL
CLIM 470n
U4050B
93 7816 e
9 (18)
U4050B
10 (18)
CNW2 1n VM Vh,Vep,dr,ni CGR 22 m + Vhs RR2 390 S13 15k RR1 b GS MICO RECO2 1 RGSA 560k RDUM1 1.34M 9 2 - + + - 10 11 + - 3 7 15 4 TIN ST RECO1 GR 39k 10 m 150 c ZH a b 200 RR1 S14 CH ZH a 68n RNW4 3.3k RS2 RS1 12k CTIN 150n 300 RNW2 2.2k RNW1 39k CNW1 220n
VM
DTMF 8
SAI LHV
26
GSA CSAO 220 m 21 SAO + CLISA 4.7 m 17 27 6 CLISA AGA CK RAGA 7.5k CK 150n 23 VL RDC 10 19 RDC 24 VC + S18 Vl C600 100 m ZL 600 RLAUT 50 Vgen
MIC1
ZM
68n
MIC2
LIMSA SQUELCH TXA AGA
S10
RSQ 100k 13
LEVSQ 12
CSQ
Figure 6. Test circuit for receiving amplifier
LIMITER NSA MUTE
5 16 25 PD GND MUTE CLIM 22
CSQ 1m
+
+ CC 10 m RIMP 1k + 14 20 VM VD RC 130k 13 V
Power supply
U4050B
28 18 IREF SWAMP RSWAMP
CIMP 100 m CM 22 m + RREF 47k 39 IM 300 mA + CD 470 m ID 2 mA CL 68n
IL
CLIM 470n
VMUTE 0.3 V
VPD 0.3 V
Rev. A2, 05-Mar-98
93 7817 e
CNW2 1n VM Vh CGR 22 m + a S14 RR1 CTIN 150n 15k GR RECO1 RECO2 3 1 a S16 RGSA 560k GSA b 26 RLAUT 50 21 SAO CSAO 220 m + S17 Vgen - + + - + - 2 4 b 200 ZH RNW4 3.3k RS2 RS1 12k 300 RR2 390 68n RNW2 2.2k RNW1 39k 220n
Rev. A2, 05-Mar-98
CNW1 GS MICO 9 7 15 TIN ST RGSA 15k RDUM1 1.34M
VM
DTMF 8
SAI LHV
MIC1 10
ZM
68n
MIC2 11
Vsao,nsa,dsao 17 27 CLISA AGA S18 6 CK CK 150n 23 VL 10 RDC RAGA 7.5k
C600 CLISA 4.7 m + 100 m ZL 600 Vl
LIMSA TXA AGA
S10
RSQ 100k
LEVSQ 12
CSQ
13
SQUELCH
+
Figure 7. Test circuit for speaker amplifier
Power supply NSA MUTE
5 16 MUTE PD 25 GND 22 IREF 19 RDC 24 28 SWAMP 18 VM 14 VD 20
S9
CSQ 1m
+ CC 10 m RIMP 1k VC CL 68n + CD + RC 130k 13V IL
LIMITER
U4050B
CLIM
CLIM VMUTE 0.3 V VPD 0.3 V
470n
RREF 47k
RSWAMP 39
IM 300 m A
+
470 m CM 22 m
CIMP 100 m ID 2 mA
U4050B
11 (18)
93 7818 e
U4050B
12 (18)
CNW2 1n Vh VM CGR 22 m + S14 RNW4 3.3k b 200 RR1 CTIN 150n TIN 7 4 1 RGSA 560k - + + - + 21 SAO - 2 15 3 ST GR RECO1 RECO2 RDUM1 1.34M 15k RS2 RS1 12k 300 RR2 390 ZH a 68n RNW2 2.2k RNW1 39k CNW1 220n GS 9 MICO
Vdtmf
RZDTMF 10k
b
CDTMF
DTMF 8
S11
a
680n
SAI LHV
26
GSA CSAO 220 m + CLISA 4.7 m C600 100 m RLAUT 50
MIC1 10
ZM
68n
MIC2 11
LIMSA TXA SQUELCH AGA
S10
RSQ 100k
17 27 6
LEVSQ 12
CLISA AGA CK CK 150n 23 VL RDC 10 19 RDC 24 VC
+ ZL 600 Vl,dd RAGA 7.5k
CSQ
13
CSQ 1m
+
Figure 8. Test circuit for DTMF amplifier
LIMITER Power supply NSA MUTE
5 16 25 PD GND IREF MUTE 22 CLIM 28 SWAMP CC 10 m
+ RIMP 1k
U4050B
18 VM 14 VD CD + RREF 47k RSWAMP 47 IM 300 mA + 470 m CM 22 m RC 130k ID 2 mA CIMP 100 m CL 68n 20 13 V IL
CLIM VMUTE 1.5 V VPD 0.3 V
470n
Rev. A2, 05-Mar-98
93 7819 e
CNW2 1n RNW2 2.2k RNW1 39k + RNW4 3.3k 200 RR1 CTIN 150n TIN 7 15 - + + - + 21 - RGSA 560k 4 1 2 3 ST GR RECO1 RECO2 RDUM1 1.34M Vgen 15k RS2 RS1 12k 300 RR2 390 ZH 68n CGR 22 m VM
CNW1 220n Vmico
Rev. A2, 05-Mar-98
GS 9 MICO
VM
DTMF 8
SAI LHV
26
GSA CSAO 220 m SAO + Vsao CLISA 4.7 m C600 100 m RLAUT 50
MIC1
10
Vmic
MIC2
11
LIMSA TXA SQUELCH AGA
RSQ 100k
LEVSQ 12
17 CLISA 27 6 AGA CK
+ Vl CK 150n 23 VL RDC 10 19 RDC 24 VC CC 10 m RAGA 7.5k ZL 600
+
CSQ 13
CSQ 1m
S20
Figure 9. Test circuit for squelch
LIMITER Poer supply NSA MUTE
5 22 GND IREF CLIM MUTE PD 16 25 28 SWAMP
+ RIMP 1k
VCSQ 1.5 V
U4050B
18 VM 14 VD CD + RREF 47k RSWAMP 39 IM 300 mA + 470 m CM 22 m ID 2 mA 20 RC 130k CIMP + 100 m CL 68n 13V IL
CLIM 470n DC DC VMUTE 0.3 V VPD 0.3 V
U4050B
93 7822 e
13 (18)
U4050B
14 (18)
CNW2 1n RNW2 2.2k RNW1 39k + RNW4 3.3k RS2 RR1 CTIN 150n TIN ST 15 - + + - + 21 - RGSA 560k 4 3 2 1 RECO1 RECO2 RDUM1 1.34M 7 GR 15k 200 300 12k RS1 ZH RR2 390 68n CGR 22 m VM CNW1 220n GS 9 MICO
VM
DTMF 8
SAI LHV
26
GSA RLAUT 50 CSAO 220 m + SAO CLISA 4.7 m
S17
MIC1 10
Vmic
MIC2
11
LIMSA TXA AGA SQUELCH
C600 100 m 17 27 6 CLISA AGA CK + S18 RAGA 7.5k CK 150n 23 VL RDC 10 19 RDC 24 VC CC 10 m + RIMP 1k ZL 600 VL
+
S10
RSQ 100k LEVSQ 12
CSQ
13
CSQ + 1m
Figure 10. Test circuit for MUTE and PD test
LIMITER Power supply NSA MUTE
5 16 MUTE IMUTE CLIM 470n VMUTE VPD IPD RSWAMP RREF 47k 39 IM 300 mA + CM 22 m + CD 470 m VD PD GND 25 22 IREF CLIM 28 SWAMP
U4050B
18 VM 14 VD IDPD 20 RC 130k
CIMP + 100 m
CL 68n
13V IL
Rev. A2, 05-Mar-98
93 7823 e
CNW2 1n VM CNW1 220n CGR 22 m + RNW4 3.3k 200 RR1 CTIN 150n TIN 7 2 - + + - + - RGSA 560k 15 3 4 1 ST RECO1 GR RECO2 RDUM1 1.34M 15k RS2 RS1 12k 300 RR2 390 ZH 68n 39K RNW2 2.2k RNW1
Rev. A2, 05-Mar-98
GS MICO 9
Vmic,Vcm
ZM 68n
VM
CMIC
1m
S19 26 GSA
b
a
DTMF 8
SAI LHV
S17 21 CSAO 220 m + SAO CLISA 4.7 m 17 27 6 CLISA AGA CK CK 150n 23 VL RDC 10 19 RDC 24 VC + RLAUT 50
b
a
MIC1
10
MIC2
11
LIMSA TXA SQUELCH AGA
C600 100 m
S10
RSQ 100k LEVSQ
12
CSQ
13
S18 RAGA 7.5k
Vl,Vlcm
ZL 600
CSQ 1m
+
LIMITER Power supply NSA MUTE
5 25 PD GND CLIM MUTE 16 22 IREF
Figure 11. Test circuit for transmit amplifier (CMRR)
CC + 10 m
RIMP 1k
U4050B
28 SWAMP 18 VM 14 VD CD + RREF 47k RSWAMP 39 IM 300 mA + 470 m CM 22 m ID 2 mA 20 RC 130k CIMP + 100 m CL 68n 13V IL
CLIM 470n VMUTE 0.3 V VPD 0.3 V
U4050B
93 7824 e
15 (18)
U4050B
Typical Curves
94 7832 e
S
Cond.: ID = 0 mA
max. curve
RC = 130 k
:
RC = 68 k (min. curve)
Figure 12. DC characteristics
94 7833 e
Figure 13. AGA characteristics
16 (18)
Rev. A2, 05-Mar-98
U4050B
Package Information
Package SO28
Dimensions in mm
18.05 17.80 9.15 8.65 7.5 7.3
2.35 0.4 1.27 28 16.51 15 0.25 0.10 0.25 10.50 10.20
technical drawings according to DIN specifications 13033
1
14
Rev. A2, 05-Mar-98
17 (18)
U4050B
Ozone Depleting Substances Policy Statement
It is the policy of TEMIC Semiconductor GmbH to 1. Meet all present and future national and international statutory requirements. 2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances ( ODSs). The Montreal Protocol ( 1987) and its London Amendments ( 1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances. TEMIC Semiconductor GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents. 1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively 2 . Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency ( EPA) in the USA 3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C ( transitional substances ) respectively. TEMIC Semiconductor GmbH can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances.
We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use TEMIC products for any unintended or unauthorized application, the buyer shall indemnify TEMIC against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. TEMIC Semiconductor GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany Telephone: 49 ( 0 ) 7131 67 2831, Fax number: 49 ( 0 ) 7131 67 2423
18 (18)
Rev. A2, 05-Mar-98

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